Existing complex programmable logic devices (CPLD), field programmable gate array (FPGA), and application specific integrated circuit (ASIC) technologies do not directly support the implementation of internal bi-directional signals without the use of a dedicated direction control signal.
A common method of implementing an asynchronous bi-directional half duplex communications link is the use of an open drain or open collector driver and a logic receiver at each end of the communications link which has a pull up resistor to a common voltage. Multiple devices can be connected to the same link. In the case of multiple devices on the same link, when one device talks, all other devices on the net receive the message. In this case, an agreed means of addressing is used so that the intended recipient knows the message is for him. At times it is desirable to isolate certain devices on such a link because multiple devices may share the same address, or there may not be enough addresses to accommodate the number of devices. Alternatively, it may be desirable to isolate a failing device from the link so that the failing device does not render the link inoperative. Many other instances arise wherein it is desirable to be able to inexpensively route and manipulate such communications links. Typically, open drain and open collector communication links can be isolated, switched and routed using analog switches. Analog switches are large and expensive, limiting the complexity of switching. Accordingly, it is desirable to be able to switch and route such signals using logic gates which could reside on a CPLD, FPGA, ASIC or other highly integrated, inexpensive device.
It is furthermore desirable to provide a method for avoiding oscillation on a self-synchronous bi-directional bus. It is furthermore desirable that such a method avoid oscillation without requiring a reduction in speed of communications on the bus.